This invention relates to the field of solid state electronics, and is particularly directed to a double lift-off process for producing a field effect transistor (FET).
As the demand for high device density and smaller features increases in the integrated circuit industry, multi-leval resist systems become more popular and have been successfully used in conjunction with optical projection aligners to print submicron features.
Self-aligned n.sup.+ implantation is effective to reduce the source parasitic resistance and consequently to increase the extrinsic transconductance of GaAs FET devices such as HEMTs (high electron mobility transistors) and MESFETs (metal semiconductor field effect transistors). However, this process requires that the Schottky gates be deposited before the implantation and therefore the threshold voltage of the device can not be adjusted. Furthermore, the Schottky gate has to be made from certain material, such as refractory silicide, that can withstand high temperature post implantation annealing.
Consequently, this process is not totally compatible to the commonly used enhancement/depletion (E/D) circuits because separate gate recessings are generally required for the E and D devices. To solve this problem, a substitutional gate process was recently proposed. This technology allows one to monitor the gate recessing and also to use regular metal instead of refractory silicide.